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All digests tagged Compiler Optimization
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Learn how progressive IR lowering transforms PyTorch layers into efficient GPU kernels. We explore the compiler stack: PyTorch $\rightarrow$ Tensor AR $\rightarrow$ Loop IR $\rightarrow$ Tile IR $\rightarrow$ CUDA, detailing fusion, normalization, and tiling for maximum performance.
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Learn how ML compilers progressively lower PyTorch graphs to efficient CUDA kernels. We explore the IR stack: from PyTorch to Loop IR, Tiling, and Kernel IR, detailing fusion and scheduling.
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The talk presents formal verification for AI-generated GPU kernels, detailing how tools like Tatwa use Z3 solvers to prove semantic equivalence between reference and optimized kernels, moving beyond the limitations of traditional testing.
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Formal verification is crucial for guaranteeing the correctness of AI-generated GPU kernels. The speaker details how tools like Tatwa prove semantic equivalence by decomposing tensor operations into scalar math primitives for solvers like Z3.
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The talk details how formal verification proves GPU kernel correctness instead of testing it. By operating at the PTX level and using SMT solvers, it addresses issues like reward hacking and non-determinism inherent in AI-generated code.
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Mega kernels fuse entire forward passes into one persistent kernel, eliminating traditional GPU overheads like global synchronization and SRAM clearing. This enables fine-grained scheduling by allowing cores to dynamically pick up slack from slower units.
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